weixin_43012678:
//实现功能：串转并，当最后一位时，输出valid_out标志，表示已转化完成
module chuan2bing#(parameter DATA_WIDTH = 8)
(
input wire clk ,
input wire rstn ,
input wire din,
input din_en,
output wire [DATA_WIDTH-1:0]dout ,
output wire valid_out
);
//*************code***********//
localparam CNT_WIDTH = (DATA_WIDTH == 1) ? 1 : $clog2(DATA_WIDTH);
reg [CNT_WIDTH-1:0] cnt;
reg [DATA_WIDTH-1:0] data_reg;
always@(posedge clk or negedge rstn)begin
if(~rstn) begin
cnt <= -1;
end else if(din_en) begin
if(cnt == DATA_WIDTH-1) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
end
end
always@(posedge clk or negedge rstn)begin
if(~rstn) begin
data_reg <= 0;
end else if(din_en) begin
data_reg <= {data_reg[DATA_WIDTH-2:0],din};
end else
data_reg <= data_reg;
end
assign dout = data_reg ;
assign valid_out = (cnt == DATA_WIDTH-1) && din_en;
//*************code***********//
endmodule